A. Field of the Invention
The present invention relates to a circuit in an optical read/write device for protecting synchronizing patterns, which interpolates the correct frame SYNC signal by estimating correct frame periods using a reference clock with fix frequency when defects occur on discs.
B. Description of the Related Art
In the reading processes for conventional optical discs, such as CDs (Compact Discs) and DVDs (Digital Versatile Disk), a laser beam is provided to scan the digital data recorded on the optical discs. Taking the CD for an example, digital data are subjected to an EFM (eight-bit to fourteen-bit modulation) signal arranged in one frame in a given format to be recorded on the CD. Each frame of digital data includes a frame SYNC signal disposed at the head of the frame, a plurality of audio data words, and error correcting bits and consists of 588 channel bits in total. The frame SYNC signal is constituted by 24 channel bits and has a specific variation pattern sufficient to be distinguished from any other digital data.
In a playing system for optical discs, the SYNC signals are used to generate a control signal for dividing frames and dividing digital data in one frame at a given unit. Therefore, the conventional read/write device for optical discs is provided with a SYNC-signal detection circuit. Also, the read/write device further includes a SYNC protecting circuit for protecting synchronizing patterns in combination with the SYNC-signal detection circuit. Accordingly, when defects occur on the discs and thus the SYNC signal is lost, a correct SYNC signal can be interpolated so as not to influence the data decoding.
FIG. 4 is a block diagram of a conventional circuit for protecting synchronizing patterns. As shown in FIG. 4, the circuit for protecting synchronizing patterns, the SYNC signal, uses the output clock (PLCK) of a PLL (Phase locked loop) device as a reference signal to estimate the interval period of the frame. However, when there are defects or scratches on the optical discs, the SYNC signal may be lost or noises may occur. In this case, the output clock of PLL device cannot be locked and a frequency shift may occur, thereby causing a calculation error for the frame SYNC signal.
FIG. 5 is a timing chart showing the frequency of output clock of PLL device shifting downwards due to the lost of SYNC signal or the noise. As shown in FIG. 5, when there are defects on the disc (i.e., the defect signal is H), the frequency of output clock of the PLL device cannot be locked and then the interpolated frame SYNC signal cannot be generated at correct period. Accordingly, the digital data processing will generate an error result. For example, the frame length of each EFM frame is 588T (1 T=I PLCK pulse). When noises occur at the (N+5) frame, the PLL device will generate an error frequency for the PLCK. In this case, the pulse number of the PLCK that are found in a predetermined window may be 560, 540, 520, etc. The correct pulse number of 588 will not be returned until the data is corrected. If data processing is performed according to this error pulse number, the system will generate mistakes in the calculated frame SYNC signal. The SYNC found signal has a constant period only when the data is correct. The real SYNC signal (REAL SYNC) is used to determine whether the found frame SYNC signal period appears repeatedly at a constant period. The In SYNC signal falls down (disable) after the real SYNC signal disappears for a few continuous frames to indicate that the period of the current frame SYNC signal is not correct. The In SYNC signal does not rise (enable) until the continuous pulses of real SYNC signal are found. Correspondingly, the frame SYNC signal is generated according to the real SYNC signal. Thus, when the real SYNC signal is correct, the frame SYNC signal and the real SYNC signal will be generated synchronously. However, when the real SYNC signal is not correct and fails to appear, the frame SYNC signal will still calculate the frame position per 588 pulses of PLCK. As shown in FIG. 5, the pulses of the frame SYNC signal will be shifted gradually at the defect region and will be synchronous with the real SYNC signal again when the real SYNC signal is found. However, due to the PLCK frequency shifted at the defect region, the counting of the frame will be error, for example at the position of (n+13).